1. Field of the Invention
This invention relates to a semiconductor device and, in particular, relates to a semiconductor device improved in strength of a bump array to which thermal stress is particularly applied among bumps that serve as external terminals of the semiconductor device, and further relates to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Semiconductor devices are widely known having a structure in which a semiconductor chip is mounted on one surface of a wiring substrate and bumps are arranged on the other surface thereof. When a semiconductor device having such a structure is used while being disposed on a mounting board, there are instances where thermal stress is applied to bumps due to a difference in thermal expansion coefficient between a wiring substrate and the mounting board to cause the bumps to fracture, thus leading to the occurrence of connection failure.
Particularly, in a semiconductor device in which a semiconductor chip is mounted so as to be offset or shifted from the center of a wiring substrate for the purpose of ensuring a space for wire bonding, greater thermal stress is applied to a bump array located at a farther position from the center of the wiring substrate in the chip shift direction due to asymmetry of the structure of the device. This will be explained for a BGA (ball grid array) semiconductor device mounted with a plurality of chips, which is illustrated in FIGS. 10 and 11.
In the mounting temperature cycle evaluation of a semiconductor device, fracture of bumps such as solder balls occurs due to the influence of stress generated by a difference in thermal expansion coefficient (α) between a wiring substrate 2 and chips 6 forming the semiconductor device or a difference in a between the semiconductor device and a non-illustrated mounting board. This fracture often occurs mainly at bumps 5 disposed at four corners or bumps 5 disposed under chip corners, which are most subjected to stress among all bumps 5 in the generally grid-shaped bump arrangement of the semiconductor device.
More specifically, in the chip shift direction (on the side A in FIG. 10), the chips 6 made of, for example, a low-α silicon are concentrated, and fixed rigidly by the wiring substrate 2 and a sealing body 10 each made of, for example, an epoxy resin having α greater than that of the silicon. Therefore, the bumps 5 disposed under the wiring substrate 2 in the chip shift direction (on the side A in FIG. 10) are largely subjected to stress generated by the difference in α as compared with the bumps 5 disposed in the other place. Particularly, a bump array 5-1 located at a position farthest from the center of the wiring substrate 2 in the chip shift direction is subjected to extremely great stress. As a result, bump fracture tends to occur at this portion and thus the lifetime of those bumps decreases, which shortens the lifetime of the semiconductor device itself.
As shown in FIG. 12, Japanese Unexamined Patent Application Publication (JP-A) No. 2001-210749 (Patent Document 1) discloses a wiring substrate wherein the size of bumps at four corners of the wiring substrate is set greater for increasing the connection strength of those bumps.
On the other hand, as shown in FIG. 13, Japanese Unexamined Patent Application Publication (JP-A) No. Hei 09-162531 (Patent Document 2) discloses a bump arrangement structure wherein the contour of a bump arrangement at the outer peripheral portions of a substrate is set concentric with the center of the substrate to thereby prevent stress from concentrating on specific bumps to cause fracture of those bumps.
These prior art structures are each considered to have some effect against the occurrence of bump fracture at the four corners of the generally grid-shaped bump arrangement, but the effect is not sufficient. This is because it is not necessarily only at the four corners of the semiconductor device where the stress tends to concentrate and cause bump fracture.
Japanese Unexamined Patent Application Publication (JP-A) No. 2005-183934 (Patent Document 3) discloses a multi-chip semiconductor device in which upper and lower chips are bump-connected to each other and the upper chip is disposed so as to be shifted relative to the lower chip, wherein the center of gravity of the upper chip is set to fall within a connecting bump region between the upper and lower chips, thereby improving the connection between the upper and lower chips. However, even if the bump connection between the upper and lower chips in the semiconductor device can be improved, no teaching is given about a measure for improving the bump connection between the semiconductor device and a mounting board.
As another known example of strengthening the bump connection, Japanese Unexamined Patent Application Publication (JP-A) No. 2000-138447 (Patent Document 4) discloses a structure in which lands on the mounting board side each have a concave-convex shape. On the other hand, Japanese Unexamined Patent Application Publication (JP-A) No. 2004-079559 (Patent Document 5) discloses a technique of shifting bump arrays by a half pitch to narrow bump intervals, thereby achieving a high-density bump arrangement.
Japanese Unexamined Patent Application Publication (JP-A) No. Hei 10-012620 (Patent Document 6) discloses a structure in which large-diameter bumps or dummy bumps are disposed as auxiliary bumps at the outer peripheral portions of a bump arrangement.